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technical note rohm?s selection operational amplifier/comparator series operational amplifiers: high voltage cmos ? input-output full swing BD7561G,bd7561sg,b d7541g,bd7541sg, bd7562f/fvm,bd7562s f/fvm, bd7542f/fvm,bd7542s f/fvm description high voltage operable cmos op-amp bd7561/ bd7541 family and bd 7562/bd7542 family integrate one or two independent input-output full swing op-amps and phase compesation capacitors on a single chip. especially, characteristics are wide operating voltage range of +5[v] +14.5[v](single power supply), low supply current and little input bias current. characteristics 1) wide operating supply voltage( 5[v] 14.5[v]) 8) internal esd protection 2) 5[v] 14.5[v](single supply) human body model (hbm) 4000[v](typ.) 2.5[v] 7.25[v](split supply) 9) wide temperature range 3) input and output full swing 40[ ] 85[ ] 4) internal phase compensation (BD7561G,bd7562 family, bd7541g,bd7542 family) 5) high slew rate (bd7561 family, bd7562 family) 40[ ] 105[ ] 6) low supply current (bd7541 family, bd7542 family) (bd7561sg,bd7562s family, bd7541sg,bd7542s family) 7) high large signal voltage gain pin assignment 1 2 3 4 8 7 5 out1 in1- in1+ vss vdd out2 in2- in2+ ch1 - + ch2 + - 6 1 2 3 5 4 in+ vss in- vdd out + - ssop5 sop8 msop8 BD7561G bd7561sg bd7541g bd7541sg bd7562f bd7562sf bd7542f bd7542sf bd7562fvm bd7562sfvm bd7542fvm bd7542sfvm dec. 2008 M 1 1 2 2 BD7561G (bd7561sg:105 ) bd7562f/fvm (bd7562sf/fvm:105 ) bd7541g (bd7541sg:105 ) bd7542f/fvm (bd7542sf/fvm:105 ) high speed low power dual single (bd7561sg operation guaranteed up to +105 ) (bd7562sf/fvm operation guaranteed up to +105 ) (bd7541sg operation guaranteed up to +105 ) (bd7542sf/fvm operation guaranteed up to +105 ) dual single
2/16 absolute maximum ratings (ta=25[ ]) parameter symbol rating unit BD7561G bd7562 f/fvm bd7541g bd7542 f/fvm bd7561sg bd7562s f/fvm bd7541sg bd7542s f/fvm supply voltage vdd-vss 15.5 v differential input voltage(*1) vid vdd-vss v input common-mode voltage range vicm (vss 0.3) (vdd 0.3) v operating temperature topr 40 85 40 105 storage temperature ts t g 55 125 maximum junction temperature tjmax 125 note: absolute maximum rating item indicates the condition which must not be exceeded. application of voltage in excess of absolute maximum rating or use out absoluted maximum rated temperature environment may c ause deterioration of characteristics. (*1) the voltage difference between inverting input and non-inverting input is the differential input voltage. then input terminal voltage is set to more then vss. electric characteristics bd7561 family, bd7562 family (unless otherwise specified vdd=+12[ v], vss=0[v], ta=25[ ] ) parameter symbol temperature range guaranteed limit unit condition BD7561G bd7561sg bd7562 f/fvm bd7562s f/fvm min. typ. max. min. typ. max. input offset voltage (*2)(*4) vio 25 - 1 9 - 1 9 mv vdd=5 14.5[v],vout=vdd/2 full range - - 10 - - 10 input offset current (*2) iio 25 - 1 - - 1 - pa - input bias current (*2) ib 25 - 1 - - 1 - pa - supply current (*4) idd 25 - 370 550 - 750 1300 a rl= all op-amps av=0[db],vdd=5[v],vin=2.5[v] rl= all op-amps av=0[db],vdd=12[v],vin=6.0[v] full range - - 600 - - 1500 25 - 440 650 - 900 1400 full range - - 700 - - 1600 high level output voltage voh 25 vdd-0.1 - - vdd-0.1 - - v rl=10[k ? ] low level output voltage vol 25 - - vss+0.1 - - vss+0.1 v rl=10[k ? ] large single voltage gain av 25 70 95 - 70 95 - db rl=10[k ? ] input common-mode voltage range vicm 25 0 - 12 0 - 12 v vdd-vss=12[v] common-mode rejection ratio cmrr 25 45 60 - 45 60 - db - power supply rejection ratio psrr 25 60 80 - 60 80 - db - output source current (*3) ioh 25 3 8 - 3 8 - ma vdd-0.4[v] output sink current (*3) iol 25 4 14 - 4 14 - ma vss+0.4[v] slew rate sr 25 - 0.9 - - 0.9 - v/ s cl=25[pf] gain bandwidth product ft 25 - 1.0 - - 1.0 - mhz cl=25[pf], av=40[db] phase margin 25 - 50 - - 50 - cl=25[pf], av=40[db] total harmonic distortion thd 25 - 0.05 - - 0.05 - % vo ut=1[vp-p],f=1[khz] (*2) absolute value (*3) under the high temperature environment, consider the power dissipation of ic when selecting the output current. when the terminal short circuits are continuously output, the output current is reduced to climb to the temperature inside ic. (*4) full range bd7561, bd7562 ta = - 4 0 [ ] +85[ ] bd7561s, bd7562s ta=-40[ ] +105[ ] electric characteristics bd7541 family, bd7542 family (unless otherwi se specified vdd=+ 12[v], vss=0[v], ta=25[ ]) parameter symbol temperature range guaranteed limit unit condition bd7541g bd7541sg bd7542 f/fvm bd7542s f/fvm min. typ. max. min. typ. max. input offset voltage (*5)(*7) vio 25 - 1 9 - 1 9 mv vdd=5 14.5[v],vout=vdd/2 full range - - 10 - - 10 input offset current (*5) iio 25 - 1 - - 1 - pa - input bias current (*5) ib 25 - 1 - - 1 - pa - supply current (*7) idd 25 - 170 300 - 340 650 a rl= all op-amps av=0[db],vdd=5[v],vin=2.5[v] rl= all op-amps av=0[db],vdd=12[v],vin=6.0[v] full range - - 400 - - 850 25 - 180 320 - 400 780 full range - - 420 - - 900 high level output voltage voh 25 vdd-0.1 - - vdd-0.1 - - v rl=10[k ? ] low level output voltage vol 25 - - vss+0.1 - - vss+0.1 v rl=10[k ? ] large single voltage gain av 25 70 95 - 70 95 - db rl=10[k ? ] input common-mode voltage range vicm 25 0 - 12 0 - 12 v vdd-vss=12[v] common-mode rejection ratio cmrr 25 45 60 - 45 60 - db - power supply rejection ratio psrr 25 60 80 - 60 80 - db - output source current (*6) ioh 25 2 4 - 2 4 - ma vdd-0.4[v] output sink current (*6) iol 25 3 7 - 3 7 - ma vss+0.4[v] slew rate sr 25 - 0.3 - - 0.3 - v/ s cl=25[pf] gain bandwidth product ft 25 - 0.6 - - 0.6 - mhz cl=25[pf], av=40[db] phase margin 25 - 50 - - 50 - cl=25[pf], av=40[db] total harmonic distortion thd 25 - 0.05 - - 0.05 - % vo ut=1[vp-p],f=1[khz] (*5) absolute value (*6) under the high temperature environment, consider the power dissipation of ic when selecting the output current. when the terminal short circuits are continuously output, the output current is reduced to climb to the temperature inside ic. (*7) full range bd7541, bd7542 ta =-40 [ ] +85[ ] bd7541s, bd7542s ta = - 4 0 [ ] +105[ ]
3/16 0 3 6 9 12 15 -60 -30 0 30 60 90 120 ambient temperature [c] output source current [ma] 0 10 20 30 40 -60 -30 0 30 60 90 120 ambient temperature [c] output voltage low [mv] 0 10 20 30 40 -60 -30 0 30 60 90 120 ambient temperature [c] output sink current [ma] 0 20 40 60 80 8 9 10 11 12 13 output voltage [v] output source current [ma] 4 8 12 16 -60 -30 0 30 60 90 120 ambient temperature [c] output voltage high [v] 0 200 400 600 800 4 8 12 16 supply voltage [v] supply current [ua] 0 20 40 60 80 100 -10123 output voltage [v] output sink current [ma] 4 8 12 16 4 8 12 16 supply voltage [v] output voltage high [v] 0 200 400 600 800 0 50 100 150 ambient temperature [c] power dissipation [mw] 0 10 20 30 40 4 8 12 16 supply voltage [v] output voltage low [mv] 0 200 400 600 800 -60 -30 0 30 60 90 120 ambient temperature [c] supply current [ua] 0 200 400 600 800 0 50 100 150 ambient temperature [c] power dissipation [mw] example of electrical characteristics bd7561 family fig.12 output sink current ? ambient temperature (vout=vdd-11.6[v]) fig.10 output source current ? ambient temperature (vout=vdd-0.4[v]) fig.11 output sink current ? output voltage ( vdd=12 [ v ]) fig.9 output source current ? output voltage (vdd=12[v]) bd7561 family bd7561 family bd7561 famil y bd7561 family bd7561 famil y bd7561 famil y bd7561 famil y bd7561 family bd7561 famil y bd7561 family bd7561 famil y bd7561 family ( )the above data is ability value of sample, it is not guaranteed. bd7561 -40[ ] +85[ ] bd7561s -40[ ] +105[ ] 14.5v 5v 12v BD7561G 105 85 25 -40 14.5v 5v 12v 105 85 25 -40 14.5v 5v 12v 105 85 25 -40 bd7561sg 105 85 25 -40 14.5v 5v 12v 105 85 25 -40 14.5v 5v 12v fig.7 output voltage low ? supply voltage ( rl=10[k ? ] ) fig.3 supply current ? supply voltage fig.4 supply current ? ambient temperature fig.5 output voltage high ? supply voltage (rl=10[k ? ]) fig.6 output voltage high ? ambient temperature (rl=10[k ? ]) fig.8 output voltage low ? ambient temperature (rl=10[k ? ]) fig.1 derating curve fig.2 derating curve supply current [ a] supply current [ a]
4/16 0 1 2 3 4 -60 -30 0 30 60 90 120 ambient temperature [c] slew rate l-h [v/us] 0 20 40 60 80 100 120 481216 supply voltage [v] common mode rejection ratio [db] -15 -10 -5 0 5 10 15 -1 0 1 2 3 4 5 6 7 8 9 1011 1213 input voltage [v] input offset voltage [mv] 0 20 40 60 80 100 1.e+00 1.e+02 1.e+04 1.e+06 1.e+08 frequency [hz] gain [db] 0 50 100 150 200 phase (deg) 0 20 40 60 80 100 120 -60 -30 0 30 60 90 120 ambient temperature [c] power supply rejection ratio [db] 60 80 100 120 140 160 -60 -30 0 30 60 90 120 ambient temperature [c] large signal voltage gain [db] -10.0 -7.5 -5.0 -2.5 0.0 2.5 5.0 7.5 10.0 -60 -30 0 30 60 90 120 ambient temperature [c] input offset voltage [mv] 0.0 0.5 1.0 1.5 2.0 -60 -30 0 30 60 90 120 ambient temperature [c] slew rate h-l [v/us] 0 20 40 60 80 100 120 -60 -30 0 30 60 90 120 ambient temperature [c] common mode rejection ratio [db] 60 80 100 120 140 160 481216 supply voltage [v] large signal voltage gain [db] -10.0 -7.5 -5.0 -2.5 0.0 2.5 5.0 7.5 10.0 4 8 12 16 supply voltage [v] input offset voltage [mv] bd7561 family bd7561 famil y bd7561 family bd7561 family bd7561 family bd7561 famil y bd7561 famil y bd7561 famil y bd7561 famil y bd7561 family bd7561 famil y bd7561 famil y fig.18 common mode rejection ratio ? supply voltage ( vdd=12 [ v ]) fig.13 input offset voltage ? supply voltage (vicm=vdd, vout=vdd/2) fig.14 input offset voltage ? ambient temperature (vicm=vdd, vout=vdd/2) fig.15 input offset voltage ? input voltage (vdd=12[v]) fig.16 large signal voltage gain ? supply voltage fig.17 large signal voltage gain ? ambient temperature fig.19 common mode rejection ratio ? ambient temperature (vdd=12[v]) fig.20 power supply rejection ratio ? ambient temperature fig.21 slew rate l-h ? ambient temperature fig.22 slew rate h-l ? ambient temperature fig.23 gain - frequency ( )the above data is ability value of sample, it is not guaranteed. bd7561 -40[ ] +85[ ] bd7561s -40[ ] +105[ ] 105 85 25 -40 105 85 25 -40 105 85 25 -40 105 85 25 -40 14.5v 5v 12v 14.5v 5v 12v 14.5v 5v 12v 14.5v 5v 12v 14.5v 5v 12v phase gain phase[deg] common mode rejection ratio [db] slew rate l-h [v/ ] slew rate h-l [v/ ]
5/16 0 200 400 600 800 1000 1200 4 8 12 16 supply voltage [v] supply current [ua] 0 200 400 600 800 1000 1200 -60-30 0 306090120 ambient temperature [c] supply current [ua] 0 20 40 60 80 8 9 10 11 12 13 output voltage [v] output source current [ma] 0 10 20 30 40 -60 -30 0 30 60 90 120 ambient temperature [c] output sink current [ma] 4 8 12 16 -60-300 306090120 ambient temperature [c] output voltage high [v] 0 20 40 60 80 100 -1 0 1 2 3 output voltage [v] output sink current [ma] 0 10 20 30 40 -60-300 306090120 ambient temperature [c] output voltage low [mv] 4 8 12 16 4 8 12 16 supply voltage [v] output voltage high [v] 0 200 400 600 800 0 50 100 150 ambient temperature [c] power dissipation [mw] 0 3 6 9 12 15 -60 -30 0 30 60 90 120 ambient temperature [c] output source current [ma] 0 10 20 30 40 4 8 12 16 supply voltage [v] output voltage low [mv] 0 200 400 600 800 0 50 100 150 ambient temperature [c] power dissipation [mw] example of electrical characteristics bd7562 family fig.12 output sink current ? ambient temperature (vout=vdd-11.6[v]) bd7562 family bd7562 family bd7562 family bd7562 famil y bd7562 famil y bd7562 famil y bd7562 famil y bd7562 famil y bd7562 family bd7562 famil y bd7562 famil y bd7562 famil y ( )the above data is ability value of sample, it is not guaranteed. bd7562 -40[ ] +85[ ] bd7562s -40[ ] +105[ ] 14.5v 5v 12v bd7562fvm 105 85 25 -40 14.5v 5v 12v 105 85 25 -40 14.5v 5v 12v 105 85 25 -40 105 85 25 -40 14.5v 5v 12v 105 85 25 -40 14.5v 5v 12v bd7562f bd7562sfvm bd7562sf fig.10 output source current ? ambient temperature (vout=vdd-0.4[v]) fig.11 output sink current ? output voltage ( vdd=12 [ v ]) fig.9 output source current ? output voltage (vdd=12[v]) fig.7 output voltage low ? supply voltage ( rl=10[k ? ] ) fig.3 supply current ? supply voltage fig.4 supply current ? ambient temperature fig.5 output voltage high ? supply voltage (rl=10[k ? ]) fig.6 output voltage high ? ambient temperature (rl=10[k ? ]) fig.8 output voltage low ? ambient temperature (rl=10[k ? ]) fig.1 derating curve fig.2 derating curve supply current [ a] supply current [ a]
6/16 0 1 2 3 4 -60 -30 0 30 60 90 120 ambient temperature [c] slew rate l-h [v/us] 0 20 40 60 80 100 120 4 8 12 16 supply voltage [v] common mode rejection ratio [db] -15 -10 -5 0 5 10 15 -1012345678910111213 input voltage [v] input offset voltage [mv] 0 20 40 60 80 100 1.e+00 1.e+02 1.e+04 1.e+06 1.e+08 frequency [hz] gain [db] 0 50 100 150 200 phase (deg) 0 40 80 120 160 200 -60 -30 0 30 60 90 120 ambient temperature [c] power supply rejection ratio [db] 60 80 100 120 140 160 -60 -30 0 30 60 90 120 ambient temperature [c] large signal voltage gain [db] -10.0 -7.5 -5.0 -2.5 0.0 2.5 5.0 7.5 10.0 -60 -30 0 30 60 90 120 ambient temperature [c] input offset voltage [mv] 0.0 0.5 1.0 1.5 2.0 -60 -30 0 30 60 90 120 ambient temperature [c] slew rate h-l [v/us] 0 20 40 60 80 100 120 -60 -30 0 30 60 90 120 ambient temperature [c] common mode rejection ratio [db] 60 80 100 120 140 160 4 8 12 16 supply voltage [v] large signal voltage gain [db] -10.0 -7.5 -5.0 -2.5 0.0 2.5 5.0 7.5 10.0 4 8 12 16 supply voltage [v] input offset voltage [mv] bd7562 family bd7562 family bd7562 famil y bd7562 famil y bd7562 family bd7562 family bd7562 famil y bd7562 famil y bd7562 famil y bd7562 family bd7562 famil y bd7562 famil y ( )the above data is ability value of sample, it is not guaranteed. bd7562 -40[ ] +85[ ] bd7562s -40[ ] +105[ ] 105 85 25 -40 105 85 25 -40 105 85 25 -40 105 85 25 -40 14.5v 5v 12v 14.5v 5v 12v 14.5v 5v 12v 14.5v 5v 12v 14.5v 5v 12v phase gain fig.18 common mode rejection ratio ? supply voltage ( vdd=12 [ v ]) fig.13 input offset voltage ? supply voltage (vicm=vdd, vout=vdd/2) fig.14 input offset voltage ? ambient temperature (vicm=vdd, vout=vdd/2) fig.15 input offset voltage ? input voltage (vdd=12[v]) fig.16 large signal voltage gain ? supply voltage fig.17 large signal voltage gain ? ambient temperature fig.19 common mode rejection ratio ? ambient temperature (vdd=12[v]) fig.20 power supply rejection ratio ? ambient temperature fig.21 slew rate l-h ? ambient temperature fig.22 slew rate h-l ? ambient temperature fig.23 gain - frequency phase[deg] slew rate l-h [v/ ] slew rate h-l [v/ ]
7/16 0 100 200 300 400 4 8 12 16 supply voltage [v] supply current [ua] 0 5 10 15 20 -60 -30 0 30 60 90 120 ambient temperature [c] output sink current [ma] 0 10 20 30 40 8 9 10 11 12 13 output voltage [v] output source current [ma] 4 8 12 16 -60 -30 0 30 60 90 120 ambient temperature [c] output voltage high [v] 0 10 20 30 40 50 -10123 output voltage [v] output sink current [ma] 0 20 40 60 80 -60 -30 0 30 60 90 120 ambient temperature [c] output voltage low [mv] 4 8 12 16 481216 supply voltage [v] output voltage high [v] 0 200 400 600 800 0 50 100 150 ambient temperature [c] power dissipation [mw] 0 2 4 6 8 10 -60 -30 0 30 60 90 120 ambient temperature [c] output source current [ma] 0 20 40 60 80 481216 supply voltage [v] output voltage low [mv] 0 100 200 300 400 -60 -30 0 30 60 90 120 ambient temperature [c] supply current [ua] 0 200 400 600 800 0 50 100 150 ambient temperature [c] power dissipation [mw] example of electrical characteristics bd7541 family bd7541 famil y bd7541 famil y bd7541 famil y bd7541 famil y bd7541 famil y bd7541 famil y bd7541 ?? bd7541 famil y bd7541 famil y bd7541 famil y bd7541 famil y ( )the above data is ability value of sample, it is not guaranteed. bd7541 -40[ ] +85[ ] bd7541s -40[ ] +105[ ] 14.5v 5v 12v bd7541g 105 85 25 -40 14.5v 25 -40 14.5v 5v 12v 105 85 25 -40 bd7541sg 105 85 25 -40 14.5v 5v 12v 105 85 25 -40 bd7541 famil y fig.12 output sink current ? ambient temperature (vout=vdd-11.6[v]) fig.10 output source current ? ambient temperature (vout=vdd-0.4[v]) fig.11 output sink current ? output voltage ( vdd=12 [ v ]) fig.9 output source current ? output voltage (vdd=12[v]) fig.7 output voltage low ? supply voltage ( rl=10[k ? ] ) fig.3 supply current ? supply voltage fig.4 supply current ? ambient temperature fig.5 output voltage high ? supply voltage (rl=10[k ? ]) fig.6 output voltage high ? ambient temperature (rl=10[k ? ]) fig.8 output voltage low ? ambient temperature (rl=10[k ? ]) fig.1 derating curve fig.2 derating curve 5v 12v 105 85 5v 12v 14.5v supply current [ a] supply current [ a]
8/16 0 20 40 60 80 100 120 -60 -30 0 30 60 90 120 ambient temperature [c] common mode rejection ratio [db] 60 80 100 120 140 160 -60 -30 0 30 60 90 120 ambient temperature [c] large signal voltage gain [db] 60 80 100 120 140 160 481216 supply voltage [v] large signal voltage gain [db] -10.0 -7.5 -5.0 -2.5 0.0 2.5 5.0 7.5 10.0 4 8 12 16 supply voltage [v] input offset voltage [mv] 0.0 0.5 1.0 1.5 2.0 -60-300 306090120 ambient temperature [c] slew rate l-h [v/us] 0 20 40 60 80 100 120 4 8 12 16 supply voltage [v] common mode rejection ratio [db] -15 -10 -5 0 5 10 15 -1012345678910111213 input voltage [v] input offset voltage [mv] 0 20 40 60 80 100 1.e+00 1.e+02 1.e+04 1.e+06 1.e+08 frequency [hz] gain [db] 0 50 100 150 200 phase (deg) 0 40 80 120 160 200 -60-30 0 306090120 ambient temperature [c] power supply rejection ratio [db] -10.0 -7.5 -5.0 -2.5 0.0 2.5 5.0 7.5 10.0 -60 -30 0 30 60 90 120 ambient temperature [c] input offset voltage [mv] 0.0 0.2 0.4 0.6 0.8 1.0 -60 -30 0 30 60 90 120 ambient temperature [c] slew rate h-l [v/us] bd7541 family ( )the above data is ability value of sample, it is not guaranteed. bd7541 -40[ ] +85[ ] bd7541s -40[ ] +105[ ] bd7541 famil y bd7541 famil y bd7541 famil y bd7541 famil y bd7541 family bd7541 famil y bd7541 family bd7541 family bd7541 family bd7541 famil y bd7541 family 105 85 25 -40 105 85 25 -40 105 85 25 -40 105 85 25 -40 14.5v 5v 12v 14.5v 5v 12v 14.5v 5v 12v 14.5v 5v 12v 14.5v 5v 12v phase gain fig.18 common mode rejection ratio ? supply voltage ( vdd=12 [ v ]) fig.13 input offset voltage ? supply voltage (vicm=vdd, vout=vdd/2) fig.14 input offset voltage ? ambient temperature (vicm=vdd, vout=vdd/2) fig.15 input offset voltage ? input voltage (vdd=12[v]) fig.16 large signal voltage gain ? supply voltage fig.17 large signal voltage gain ? ambient temperature fig.19 common mode rejection ratio ? ambient temperature (vdd=12[v]) fig.20 power supply rejection ratio ? ambient temperature fig.21 slew rate l-h ? ambient temperature fig.22 slew rate h-l ? ambient temperature fig.23 gain - frequency phase[deg] slew rate l-h [v/ ] slew rate h-l [v/ ]
9/16 0 200 400 600 800 4 8 12 16 supply voltage [v] supply current [ua] 0 5 10 15 20 -60 -30 0 30 60 90 120 ambient temperature [c] output sink current [ma] 0 10 20 30 40 8 9 10 11 12 13 output voltage [v] output source current [ma] 4 8 12 16 -60 -30 0 30 60 90 120 ambient temperature [c] output voltage high [v] 0 10 20 30 40 50 -10123 output voltage [v] output sink current [ma] 0 20 40 60 80 -60 -30 0 30 60 90 120 ambient temperature [c] output voltage low [mv] 4 8 12 16 4 8 12 16 supply voltage [v] output voltage high [v] 0 200 400 600 800 0 50 100 150 ambient temperature [c] power dissipation [mw] 0 2 4 6 8 10 -60 -30 0 30 60 90 120 ambient temperature [c] output source current [ma] 0 20 40 60 80 481216 supply voltage [v] output voltage low [mv] 0 200 400 600 800 -60 -30 0 30 60 90 120 ambient temperature [c] supply current [ua] 0 200 400 600 800 050100150 ambient temperature [c] power dissipation [mw] example of electrical characteristics bd7542 family fig.12 output sink current ? ambient temperature (vout=vdd-11.6[v]) fig.6 output voltage high ? ambient temperature (rl=10[k ? ]) bd7542 famil y bd7542 famil y bd7542 famil y bd7542 family bd7542 famil y bd7542 family bd7542 famil y bd7542 famil y bd7542 famil y bd7542 famil y bd7542 family bd7542 famil y ( )the above data is ability value of sample, it is not guaranteed. bd7561 -40[ ] +85[ ] bd7561s -40[ ] +105[ ] 14.5v 5v 12v bd7542f 105 85 25 -40 14.5v 5v 12v 105 85 25 -40 14.5v 5v 12v 105 85 25 -40 bd7542sfvm 105 85 25 -40 14.5v 5v 12v 105 85 25 -40 14.5v 5v 12v bd7542fvm bd7542sf fig.10 output source current ? ambient temperature (vout=vdd-0.4[v]) fig.11 output sink current ? output voltage ( vdd=12 [ v ]) fig.9 output source current ? output voltage (vdd=12[v]) fig.7 output voltage low ? supply voltage ( rl=10[k ? ] ) fig.3 supply current ? supply voltage fig.4 supply current ? ambient temperature fig.5 output voltage high ? supply voltage (rl=10[k ? ]) fig.8 output voltage low ? ambient temperature (rl=10[k ? ]) fig.1 derating curve fig.2 derating curve supply current [ a] supply current [ a]
10/16 0 20 40 60 80 100 120 -60 -30 0 30 60 90 120 ambient temperature [c] common mode rejection ratio [db] 60 80 100 120 140 160 4 8 12 16 supply voltage [v] large signal voltage gain [db] 0 20 40 60 80 100 120 4 8 12 16 supply voltage [v] common mode rejection ratio [db] 0 40 80 120 160 200 -60 -30 0 30 60 90 120 ambient temperature [c] power supply rejection ratio [db] 0.0 0.5 1.0 1.5 2.0 -60-300 306090120 ambient temperature [c] slew rate l-h [v/us] -15 -10 -5 0 5 10 15 -1012345678910111213 input voltage [v] input offset voltage [mv] 0 20 40 60 80 100 1.e+00 1.e+02 1.e+04 1.e+06 1.e+08 frequency [hz] gain [db] 0 50 100 150 200 phase (deg) 60 80 100 120 140 160 -60 -30 0 30 60 90 120 ambient temperature [c] large signal voltage gain [db] -10.0 -7.5 -5.0 -2.5 0.0 2.5 5.0 7.5 10.0 -60 -30 0 30 60 90 120 ambient temperature [c] input offset voltage [mv] 0.0 0.2 0.4 0.6 0.8 1.0 -60 -30 0 30 60 90 120 ambient temperature [c] slew rate h-l [v/us] -10.0 -7.5 -5.0 -2.5 0.0 2.5 5.0 7.5 10.0 481216 supply voltage [v] input offset voltage [mv] bd7542 family bd7542 famil y bd7542 famil y bd7542 famil y bd7542 famil y bd7542 famil y bd7542 family bd7542 famil y bd7542 famil y bd7542 famil y bd7542 famil y bd7542 famil y ( )the above data is ability value of sample, it is not guaranteed. bd7561 -40[ ] +85[ ] bd7561s -40[ ] +105[ ] 105 85 25 -40 105 85 25 -40 105 85 25 -40 105 85 25 -40 14.5v 5v 12v 14.5v 5v 12v 14.5v 5v 12v 14.5v 5v 12v 14.5v 5v 12v phase gain fig.18 common mode rejection ratio ? supply voltage ( vdd=12 [ v ]) fig.13 input offset voltage ? supply voltage (vicm=vdd, vout=vdd/2) fig.14 input offset voltage ? ambient temperature (vicm=vdd, vout=vdd/2) fig.15 input offset voltage ? input voltage (vdd=12[v]) fig.16 large signal voltage gain ? supply voltage fig.17 large signal voltage gain ? ambient temperature fig.19 common mode rejection ratio ? ambient temperature (vdd=12[v]) fig.20 power supply rejection ratio ? ambient temperature fig.21 slew rate l-h ? ambient temperature fig.22 slew rate h-l ? ambient temperature fig.23 gain - frequency phase[deg] slew rate l-h [v/ ] slew rate h-l [v/ ] large signal voltage gain [db]
11/16 vio |vf1| = 1+rf/rs [v] a v |vf2-vf3| = 2 (1+rf/rs) [db] 20log cmrr |vf4-vf5| = 1.8 (1+rf/rs) [db] 20log psrr |vf6-vf7| = 3.8 (1+rf/rs) [db] 20log schematic diagram test circuit1 null method vdd,vss,ek,vicm unit : [v] parameter vf s1 s2 s3 vdd vss ek vicm calculation input offset voltage vf1 on on off 12 0 -6 12 1 large signal voltage gain vf2 on on on 12 0 -0.5 6 2 vf3 -11.5 common-mode rejection ratio (input common-mode voltage range) vf4 on on off 12 0 -6 0 3 vf5 12 power supply rejection ratio vf6 on on off 5 0 -2.5 0 4 vf7 14.5 calculation 1. input offset voltage (vio) 2. large signal voltage gain (av) 3. common-mode rejection ratio (cmrr) 4. power supply rejection ratio (psrr) fig.2 test circuit 1 (one channel only) fig1. schematic diagram vdd rf =50[k ? ] ri=1[m ? ] 0.015[ f] rs 50[ ? ] sw2 rl sw3 500[k ? ] 500[k ? ] 0.01[ f] e k 15[v] du t vss vrl 50[k ? ] vicm sw1 0.015[ f] ri=1[m ? ] vo v f rs 50[ ? ] 1000[pf] 0.1[ f] -15[v] null +
12/16 test circuit2 switch condition unit : [v] sw no. sw 1 sw 2 sw 3 sw 4 sw 5 sw 6 sw 7 sw 8 sw 9 sw 10 sw 11 sw 12 supply current off off on off on off off off off off off off maximum output voltage rl=10 [k ? ] off on off off on off off on off off on off output current off on off off on off off off off on off off slew rate off off on off off off on off on off off on maximum frequency on off off on on off off off on off off on test circuit3 channel separation v ? ] r1=1[k ? ] vdd vss vout1 =1[vrms] v ? ] r1//r2 r1//r2 r1=1[k ? ] sw1 sw2 sw 9 sw1 0 sw11 sw 8 sw5 sw6 sw7 c l sw1 2 sw4 sw3 r1 1[k ? ] r2 100[k ? ] r l gnd vdd=3[v] v o vin- vin+ fig4. slew rate input output wave fig5. test circuit3 fig3. test circuit2 vout [v] 12[v] 0[v] v t vin [v] 12[v] 0[v] 12[v p-p ] t t sr= v / t input waveform output waveform
13/16 description of electrical characteristics described here are the terms of electric c haracteristics used in this technical note. items and symbols used are also shown. note that item name and symbol and their meaning may differ from those on another manufacture ?s document or general document . 1. absolute maximum ratings absolute maximum rating item indicates the condition which must not be exceeded. application of voltage in excess of absolute maximum rating or use out of absolute maximum rated temper ature environment may cause deter ioration of characteristics. 1.1 power supply voltage vdd/vss indicates the maximum voltage that can be applied between the posit ive power supply terminal and negative power supply terminal without deterioration or destruction of characteristics of internal circuit. 1.2 differential input voltage vid indicates the maximum voltage that can be applied between non-invert ing terminal and inverting terminal without deterioration a nd destruction of characteristics of ic. 1.3 input common-mode voltage range vicm indicates the maximum voltage that can be applied to non-inverting terminal and inverting terminal without deterioration or des truction of characteristics. input common-mode voltage range of the maxi mum ratings not assure normal operation of ic. when normal operation of ic is desired, the input common-mode voltage of characteristics item must be followed. 1.4 power dissipation pd indicates the power that can be consumed by sp ecified mounted board at the ambient temperature 25 (normal temperature). as for package product, pd is determined by the temperature that can be permitted by ic chip in the package maximum junction temperature and thermal resistance of the package. 2. electrical characteristics item 2.1 input offset voltage vio indicates the voltage difference between non-inverting terminal and inverting terminal. it can be translated into the input v oltage difference required for setting the output voltage at 0 [v]. 2.2 input offset current iio indicates the difference of input bias current between non-inverting terminal and inverting terminal. 2.3 input bias current ib indicates the current that flows into or out of the input te rminal. it is defined by the average of input bias current at non -inverting terminal and input bias current at inverting terminal. 2.4 circuit current icc indicates the ic current that flows under specified conditions and no-load steady status. 2.5 high level output voltage / low level output voltage voh/vol indicates the voltage range that can be output by the ic u nder specified load condition. it is typically divided into high-le vel output voltage and low-level output voltage. high-level output voltage indicates the upper limit of output voltage. low-level output voltage i ndicates the lower limit. 2.6 large signal voltage gain av indicates the amplifying rate (gain) of output voltage agai nst the voltage difference between non-inverting terminal and inve rting terminal. it is normally the amplifying rate (gain) with reference to dc voltage. av = (output voltage fluctuation) / (input offset fluctuation) 2.7 input common-mode voltage range vicm indicates the input voltage range where ic operates normally. 2.8 common-mode rejection ratio cmrr indicates the ratio of fluctuation of input offset voltage when in-phase input voltage is changed. it is normally the fluctua tion of dc. cmrr change of input common-mode voltage / input offset fluctuation 2.9 power supply rejection ratio psrr indicates the ratio of fluctuation of input offset volt age when supply voltage is changed. it is normally the fluctuation of dc. psrr change of power supply voltage / input offset fluctuation 2.10 channel separation cs indicates the fluctuation of input offset voltage or that of output voltage with reference to the change of output voltage of driven channel. 2.11 slew rate sr indicates the time fluctuation ratio of voltage output when step input signal is applied. 2.12 unity gain frequency ft indicates a frequency where the voltage gain of op-amp is 1. 2.13 total harmonic distortion + noise thd n indicates the fluctuation of input offset voltage or that of output voltage with reference to the change of output volta ge of driven channel. 2.14 input referred noise voltage vn indicates a noise voltage generated inside the operatio nal amplifier equivalent by ideal voltage source connected in series with input terminal.
14/16 derating curve power dissipation (total loss) indicates the power that can be consumed by ic at ta=25 (normal temperature).ic is heated when it consumed power, and the temperature of ic ship becomes higher than ambient temperature. the temperature that can be accepted by ic chip depends on circuit configuration, ma nufacturing process, and consumable power is limited. power dissipation is determined by the temperatur e allowed in ic chip (maximum junction temperature) and thermal resistance of package (heat dissipation capability). the maximum junction temperature is typicall y equal to the maxi mum value in the storage package (heat dissipation capability). the maximum junction temperature is typically equal to the maximum value in the storage temperature range. heat generated by consumed power of ic radiates from the mold resin or lead frame of the package. the parameter which indicates this heat dissipation capab ility (hardness of heat release) is called thermal resistance , represented by the symbol j-a[ /w]. the temperature of ic inside the package ca n be estimated by this thermal resistance. fig.6 (a) shows the model of thermal resistance of the package. thermal resistance ja, ambient temperature ta, junction temperature tj, and power dissipation pd can be calculated by the equation below : ja (tj ta) / pd [ /w] ????? derating curve in fig.6 (b) indicates power that can be consumed by ic with reference to ambient temperature. power that can be consumed by ic begins to attenuate at certain ambient temperature. this gradient iis determined by thermal resistance ja. thermal resistance ja depends on chip size, power consumption, package, ambient temperature, package condition, wind velocity, etc even when the same of package is used. thermal reduction curve indicates a reference value measured at a specified condition. fig7(c)-(f) show a derating curve for an example of bu 7561family, bu 7562family, 7541family, 7542family. when using the unit above ta=25[ ], subtract the value above per degree[ ]. permissible dissipation is the value when fr4 glass epoxy board 70[mm] 70[mm] 1.6[mm] (cooper foil area below 3[ ]) is mounted. *8 *9 *10 unit 5.4 6.2 4.8 [mw/ ] (a) thermal resistance (b) derating curve fig.6 thermal resistance and derating 0 200 400 600 800 050100150 ambient temperature [ ] power dissipation [mw ] . 85 0 200 400 600 800 1000 0 50 100 150 ambient temperature [ ] power dissipation [mw] . 85 0 200 400 600 800 050100150 ambient temperature [ ] power dissipation [mw ] . bd7541sg(*8) 105 0 200 400 600 800 1000 0 50 100 150 ambient temperature [ ] power dissipation [mw ] . 105 (c) BD7561G bd7541g (d) bd7562f/fvm bd7542f/fvm (e) bd7561sg bd7541sg (f) bd7562s f/fvm bd7542s f/fvm bd7561sg(*8) BD7561G(*8) bd7541g(*8) 540[mw] 620[mw] 480[mw] 540[mw] bd7562f(*9) bd7542f(*9) bd7562fvm(*10) bd7542fvm(*10) 620[mw] 480[mw] bd7562sf(*9) bd7542sf(*9) bd7562sfvm(*10) bd7542sfvm(*10) fig.7 derating curve 0 ?? ta[ ] p2 p1 25 125 75 150 100 50 lsi M [w] pd(max) tj(max) ja2 ja1 ja2 < ja1 bd7561/bd7541 tj(max) ambient temperature ta [ ] power dissipation of lsi [w] ??`? ta[ ] ?? ta[ ] ??? tj[ ] M p[w] ja (tj ta) / pd [ /w] chip surface temperature tj [ ] power dissipation p [w] ambient temperature ta [ ] package surface temperature [ ]
15/16 cautions on use 1) absolute maximum ratings absolute maximum ratings are the values which indicate the limits, within which the given voltage range can be safely charged to the terminal. however, it does not guar antee the circuit operation. 2) applied voltage to the input terminal for normal circuit operation of voltage comparator, please input voltage for its input terminal within input common mode voltage vdd+0.3[v]. then, regardless of power supply volt age,vss-0.3[v] can be applied to input terminals without deterioration or des truction of its characteristics. 3) operating power supply (split power supply/single power supply) the voltage comparator operates if a given level of voltage is applied between vdd and vss. therefore, the op erational amp lifier can be operated under single power supply or split power supply. 4) power dissipation (pd) if the ic is used under excessive power dissipation. an increase in the chip temperature will cause deterioration of the radical characteristics of ic. for example, reduction of current capability. take c onsideration of the effective power dissipation and thermal design with a sufficient margin. pd is re ference to the provided power dissipation curve. 5) short circuits between pins and incorrect mounting short circuits between pins and incorrect mounting when mounting the ic on a printed circuits board, take notice of the directi on and positioning of the ic. if ic is mounted erroneously, it may be damaged. also, when a foreign object is inserted between output, between output and vdd terminal or vss terminal wh ich causes short circuit, the ic may be damaged. 6) using under strong electromagnetic field be careful when using the ic under strong electromagnetic field because it may malfunction. 7) usage of ic when stress is applied to the ic through warp of the printed circuit board, the characteristics may fluctuate due to the piezo effect. be careful of the warp of the printed circuit board. 8) testing ic on the set board when testing ic on the set board, in cases where t he capacitor is connected to the low impedance, make sure to discharge per fabrication because there is a possibility that ic may be damaged by stress. when removing ic from the set board, it is essential to cut supply voltage. as a countermeasure against the stat ic electricity, observe proper groun ding during fabrication process and take due care when carrying and storage it. 9) the ic destruction caused by capacitive load the transistors in circuits may be damaged when vdd te rminal and vss terminal is s horted with the charged output terminal capacitor. when ic is used as a oper ational amplifier or as an application circuit, where oscillation is not activated by an output capac itor, the output capacitor must be kept below 0.1[ f] in order to prevent the damage mentioned above. 10) decupling capacitor insert the deculing capacitance between vdd and vss , for stable operation of operational amplifier. 11) latch up be careful of input vltage that exceed the vdd and vss. when cmos device have sometimes occur latch up operation. and protect the ic from abnormaly noise.
16/16 dimensions model number construction packing specification reference ssop5 sop8 msop8 when you order , please order in times the amount of package quantity . packing specification name ssop5 tr 3000 sop8 e2 2500 msop8 tr 3000 package quantity embossed carrier tape reel direction of feed 1pin 1234 1234 1234 1234 1234 1234 1234 reel direction of feed 1pin 1234 1234 1234 1234 1234 1234 1234 reel 1pin x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x direction of feed reel direction of feed 1pin x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x sop8 ssop5 ? ??` ? g : ssop5 ? f : sop8 ? fvm : msop8 ? bd7561 bd7561s ? bd7541 bd7541s ? bd7562 bd7562s ? bd7542 bd7542s d 7 5 6 2 s f e 2 b - product name package type e2 embossed tape on reel with pin 1 near far when pulled out tr embossed tape on reel with pin 1 near far when pulled out ? specify the product by the model number when placing an order. ? make sure of the combinations of items. ? start with the leftmost space without leaving any empty space between characters. catalog no.08t880a '08.12 rohm ? - (unit:mm)
appendix1-rev3.0 thank you for your accessing to rohm product informations. more detail product informations and catalogs are available, please contact your nearest sales office. rohm customer support system the americas / europe / asia / japan contact us : webmaster@ rohm.co. jp www.rohm.com copyright ? 2008 rohm co.,ltd. 21 saiin mizosaki- cho, ukyo-ku, kyoto 615-8585, japan tel : +81-75-311-2121 fax : +81-75-315-0172 appendix notes no copying or reproduction of this document, in part or in whole, is permitted without the consent of rohm co.,ltd. the content specified herein is subject to change for improvement without notice. the content specified herein is for the purpose of introducing rohm's products (hereinafter "products"). if you wish to use any such product, please be sure to refer to the specifications, which can be obtained from rohm upon request. examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the information specified in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, rohm shall bear no respon- sibility for such damage. the technical information specified herein is intended only to show the typical functions of and examples of application circuits for the products. rohm does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by rohm and other parties. rohm shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. the products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). the products are not designed to be radiation tolerant. while rohm always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possi bility of physical injury, fire or any other damage caused in the event of the failure of any product, such as derating, redundancy, fire control and fail-safe designs. rohm shall bear no responsibility whatsoever for your use of any product outside of the prescribed scope or not in accordance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which re quires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). rohm shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specified herein that may be controlled under the f oreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law.

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